大师作文网有关DSP翻译,懂英文的来!谢谢
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有关DSP翻译,懂英文的来!谢谢
Example 7–56. SRCCD Instruction With a 3-Cycle Latency
RPTB endloop–1
...
SRCCD *AR3, ALEQ ;This ensures that current value of
NOP ; BRC will be written to memory.
NOP
NOP
endloop:
There is also a 5-to-6-cycle latency when writing a new value to BRC from within
a RPTB loop. The latencies described in Table 7–25 are relevant only if BRC
is modified while a RPTB loop is active. See Example 7–57 for details.
Table 7–25. Latencies for Updating BRC From Within an RPTB Loop
Instruction Latency
STM #lk, BRC
ST #lk, BRC
MVDK Smem, BRC
MVMD MMR, BRC
The next 5 instruction words must not contain
the last instruction in the RPTB loop.
All other instructions that modify
BRC
The next 6 instruction words must not contain
the last instruction in the RPTB loop.
Example 7–57. Modifying BRC From Within an RPTB Loop
RPTB endloop–1
...
XC 2, Condition ; If Condition is evaluated as
MVDK 5h, BRC ; true, write the new count value
; to BRC.
LD *AR1+, A ; These six instructions provide
ADD *AR2–, A ; sufficient latency for the new
SUB *AR3+, A ; BRC value to take effect before
LD *AR4+, T ; the next iteration begins.
MPYA A
STL A, *AR3+
endloop:
7.5.8.2 Deactivating the Block-Repeat Active Flag (BRAF)
The C54x DSP sets the block-repeat active flag (BRAF) to 1 to indicate that
the repeat-block loop is active. BRAF is set or cleared in the decode stage of
the first instruction of the repeat-block loop during the last loop iteration
(BRC = 0). BRAF is tested by the device at the end of each loop iteration to
determine whether the next prefetch will be from the top of the loop or not.
270
麻烦哪位大侠帮忙翻译下,翻译错误一些没关系,但是要和原本的的格式对应一点,看起来漂亮一点就行
Example 7–56. SRCCD Instruction With a 3-Cycle Latency
RPTB endloop–1
...
SRCCD *AR3, ALEQ ;This ensures that current value of
NOP ; BRC will be written to memory.
NOP
NOP
endloop:
There is also a 5-to-6-cycle latency when writing a new value to BRC from within
a RPTB loop. The latencies described in Table 7–25 are relevant only if BRC
is modified while a RPTB loop is active. See Example 7–57 for details.
Table 7–25. Latencies for Updating BRC From Within an RPTB Loop
Instruction Latency
STM #lk, BRC
ST #lk, BRC
MVDK Smem, BRC
MVMD MMR, BRC
The next 5 instruction words must not contain
the last instruction in the RPTB loop.
All other instructions that modify
BRC
The next 6 instruction words must not contain
the last instruction in the RPTB loop.
Example 7–57. Modifying BRC From Within an RPTB Loop
RPTB endloop–1
...
XC 2, Condition ; If Condition is evaluated as
MVDK 5h, BRC ; true, write the new count value
; to BRC.
LD *AR1+, A ; These six instructions provide
ADD *AR2–, A ; sufficient latency for the new
SUB *AR3+, A ; BRC value to take effect before
LD *AR4+, T ; the next iteration begins.
MPYA A
STL A, *AR3+
endloop:
7.5.8.2 Deactivating the Block-Repeat Active Flag (BRAF)
The C54x DSP sets the block-repeat active flag (BRAF) to 1 to indicate that
the repeat-block loop is active. BRAF is set or cleared in the decode stage of
the first instruction of the repeat-block loop during the last loop iteration
(BRC = 0). BRAF is tested by the device at the end of each loop iteration to
determine whether the next prefetch will be from the top of the loop or not.
270
麻烦哪位大侠帮忙翻译下,翻译错误一些没关系,但是要和原本的的格式对应一点,看起来漂亮一点就行
例子7–56.与3周期潜伏的SRCCD指示
RPTB endloop–1
…
SRCCD *AR3,ALEQ; 这保证那个当前值
NOP; BRC给记忆将被写.
NOP
NOP
endloop ：当写新的价值给BRC从的内部时,There也是5对6周期潜伏a RPTB圈.在表描述的潜伏7–25里是相关的,只有当BRC 修改过的is,当RPTB圈是活跃的时.看见例子7–57关于细节.
Table 7–25.更新的BRC潜伏从RPTB圈的内部Instruction潜伏
STM #lk,BRC
ST #lk,BRC
MVDK Smem,BRC
MVMD MMR,BRC
The其次5个做指令的字不能包含
the持续在RPTB圈的指示.
All修改的其他指示
BRC
The其次6个做指令的字不能包含
the持续在RPTB圈的指示.
Example 7–57.从RPTB圈的内部修改BRC
RPTB endloop–1
…
XC 2,情况; 如果情况被评估
MVDK 5h,BRC; 配齐,写新的计数值
; 对BRC.
LD *AR1+,A; 这六指示提供
ADD *AR2–,A; 新的充足的潜伏
SUB *AR3+,A; 以前起作用的BRC价值
LD *AR4+,T; 下叠代开始.
MPYA A
STL A,*AR3+
endloop ：
7.5.8.2撤销阻拦重复活跃旗子(BRAF)
The C54x DSP设置阻拦重复活跃旗子(BRAF)到1表明那
the重复阻拦圈是活跃的.BRAF在解码阶段被设置或被清除 在最后圈叠代期间,the第一指示重复阻拦圈 (BRC = 0).BRAF由设备测试在每圈叠代的结尾对的determine是否下先提取将是从圈的顶端.
270
RPTB endloop–1
…
SRCCD *AR3,ALEQ; 这保证那个当前值
NOP; BRC给记忆将被写.
NOP
NOP
endloop ：当写新的价值给BRC从的内部时,There也是5对6周期潜伏a RPTB圈.在表描述的潜伏7–25里是相关的,只有当BRC 修改过的is,当RPTB圈是活跃的时.看见例子7–57关于细节.
Table 7–25.更新的BRC潜伏从RPTB圈的内部Instruction潜伏
STM #lk,BRC
ST #lk,BRC
MVDK Smem,BRC
MVMD MMR,BRC
The其次5个做指令的字不能包含
the持续在RPTB圈的指示.
All修改的其他指示
BRC
The其次6个做指令的字不能包含
the持续在RPTB圈的指示.
Example 7–57.从RPTB圈的内部修改BRC
RPTB endloop–1
…
XC 2,情况; 如果情况被评估
MVDK 5h,BRC; 配齐,写新的计数值
; 对BRC.
LD *AR1+,A; 这六指示提供
ADD *AR2–,A; 新的充足的潜伏
SUB *AR3+,A; 以前起作用的BRC价值
LD *AR4+,T; 下叠代开始.
MPYA A
STL A,*AR3+
endloop ：
7.5.8.2撤销阻拦重复活跃旗子(BRAF)
The C54x DSP设置阻拦重复活跃旗子(BRAF)到1表明那
the重复阻拦圈是活跃的.BRAF在解码阶段被设置或被清除 在最后圈叠代期间,the第一指示重复阻拦圈 (BRC = 0).BRAF由设备测试在每圈叠代的结尾对的determine是否下先提取将是从圈的顶端.
270