大师作文网请帮我用Verilog设计一个计数器
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请帮我用Verilog设计一个计数器
计数范围：271
异步清零
同步置位功能
同步预置数功能
计数使能功能
加减计数功能
当为加法计数器时,要有溢出进位
当为减法计数器时,要有借位标志
when
Reset =0, out= 0…0
Preset=0, out=11..1
Load =1, out = in
when
Count_en=1, and
Up_down=1, out = out +1
Up_down =0, out=out-1
when
Out = 11…1 or out = 00…0,
Carry_out = 1
Otherwise
Carry_out = 0
计数范围：271
异步清零
同步置位功能
同步预置数功能
计数使能功能
加减计数功能
当为加法计数器时,要有溢出进位
当为减法计数器时,要有借位标志
when
Reset =0, out= 0…0
Preset=0, out=11..1
Load =1, out = in
when
Count_en=1, and
Up_down=1, out = out +1
Up_down =0, out=out-1
when
Out = 11…1 or out = 00…0,
Carry_out = 1
Otherwise
Carry_out = 0
你关于carry的描述和你的伪代码不一致啊.
module counter(
input clk, rst, prst, load, cnt_en, up_down,
input [8:0] in,
output reg [8:0] out,
output reg carry_out);
always@(posedge clk or negedge rst)
if(~rst) begin
carry_out
module counter(
input clk, rst, prst, load, cnt_en, up_down,
input [8:0] in,
output reg [8:0] out,
output reg carry_out);
always@(posedge clk or negedge rst)
if(~rst) begin
carry_out